1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a non-volatile memory and a fabricating method thereof.
2. Description of Related Art
As techniques for manufacturing deep sub-micron semiconductors start to mature, physical dimensions of devices are reduced little by little. Hence, the size of memory cells in memory devices has become smaller and smaller. In another aspect, since information electronic products including computers, mobile phones, digital cameras, and personal digital assistants (PDA) are required to process and store an increasing amount of data, memory capacity required by these information electronic products is increased accordingly. In order to satisfy the formidable demand for the memory devices with compactness and large memory volume, producing small-sized and highly-integrated memory devices featuring fine quality is one of the common goals to be achieved by this industry.
Among the memory devices, a non-volatile memory is capable of safeguarding written data even after the power supplied to the non-volatile memory is cut off, and therefore the non-volatile memory has been extensively applied to personal computers and electronic equipments.
The non-volatile memory can be classified into a mask read only memory (ROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (E2PROM), and a one-time-programmable ROM (OTPROM) based on the way by which data are stored in the memory.
U.S. Pat. No. 6,678,190 discloses a non-volatile memory in which the formation of multiple polysilicon layers is not required. Instead, two serially connected p-type metal-oxide-semiconductor (MOS) transistors respectively disposed on an N well as a select gate and a floating gate are disposed in the non-volatile memory. Since it is not necessary to form a control gate in the non-volatile memory, a fabricating process of the non-volatile memory can be integrated with a fabricating process of a complementary MOS transistor, thereby reducing fabricating costs.
US Patent Publication No. 2004/0159881 discloses a non-volatile memory device in which the Stacked SiGe—Si floating gate is formed to accumulate charges away from the tunneling gate oxide. US Patent Publication No. 2006/0043463 discloses a floating gate in which an altered floating gate material is used to increase barrier height between floating gate and tunneling dielectric layer.
Nonetheless, in the above-mentioned non-volatile memory, charges are stored in the floating gate for determining digital information. During programming operation of the non-volatile memory, the charges cross over a gate dielectric layer disposed under the floating gate, and the charges then enter into the floating gate. Hence, the gate dielectric layer is apt to be damaged, which leads to occurrence of current leakage. Besides, the gate dielectric layer is indispensable to be shrunk as the process scaling proceeding, in order to keep gate-driving capabilities of transistors. In particular, divot regions are formed in interfaces of the gate dielectric layer and corners of an isolation structure, such as a shallow trench isolation structure, in the device. The gate dielectric layer in the divot regions is relatively thin, and the gate-stored charges are prone to leak therein. Therefore, data retention efficacy of the memory device by using of the generic oxide process in a given process is vulnerably likely to be reduced thereby. Additionally, as integrity of the device increases and the thickness of the gate dielectric layer below the floating gate is reduced, the current leakage tends to be even deteriorated. As such, it is crucial to improve the data retention efficacy of the memory device.